Superconducting nanowire memory array achieves significantly lower error rate

 
Quantum computers, systems that process information leveraging quantum mechanical effects, will require faster and energy-efficient memory components, which will allow them to perform well on complex tasks. Superconducting memories are promising memory devices that are made from superconductors, materials that conduct electricity with a resistance of zero when cooled below a critical temperature.

These memory devices could be faster and consume significantly less energy than existing memories based on superconductors. Despite their potential, most existing superconducting memories are prone to errors and are difficult to scale up to create larger systems containing several memory cells.

Researchers at Massachusetts Institute of Technology (MIT) recently developed a new scalable superconducting memory that is based on nanowires, one-dimensional (1D) nanostructures with unique optoelectronic properties. This memory, introduced in a paper published in Nature Electronics, was found to be less prone to errors than many other superconducting nanowire-based memories introduced in the past.

"Scalable superconducting memory is required for the development of low-energy superconducting computers and fault-tolerant quantum computers," Owen Medeiros, Matteo Castellani, and their colleagues wrote in their paper.

"Conventional superconducting logic-based memory cells possess a large footprint that limits scaling; nanowire-based superconducting memory cells, although more compact, have high error rates, which hinders integration into large arrays. We report a 4 × 4 superconducting nanowire memory array that is designed for scalable row–column operations and has a functional density of 2.6 Mbit cm⁻²."

The team's nanowire-based superconducting memory

As part of their study, the researchers built a small and compact array of superconducting memory cells using nanowires. Each cell essentially consists of a superconducting nanowire loop, with two switches and a kinetic inductor.

The resistance of the two superconducting switches changes along with the temperature. The kinetic inductor, on the other hand, resists changes in electrical current, allowing it to flow following predictable patterns and supporting the memory's stable operation.

"Each memory cell is based on a nanowire loop consisting of two temperature-dependent superconducting switches and a variable kinetic inductor," wrote the researchers. "The arrays operate at 1.3 K, where we implement and characterize multiflux quanta state storage and destructive read-out. By optimizing the write- and read-pulse sequences, we minimize bit errors and maximize operating margins."

The memory developed by Medeiros, Castellani and their colleagues writes and reads information via carefully timed electrical pulses that are sent to specific cells. These pulses briefly heat one of the nanowire switches, which increases its resistance and injects a magnetic flux into the loop.

This magnetic flux encodes different data values (0 or 1). Once the pulse ends and the nanowire is cooled back down, it goes back to a superconducting state, trapping the information-containing flux into the nanowire loop.

Bringing superconducting memories closer to their practical use

In initial tests, the new nanowire-based superconducting memory array was found to perform remarkably well, storing information while making approximately 1 error in 100,000 operations. This is a significantly lower error rate than that exhibited by most other superconducting memories introduced over the past few years.

"We achieve a minimum bit error rate of 10⁻⁵," wrote the authors. "We also use circuit-level simulations to understand the memory cell's dynamics, performance limits and stability under varying pulse amplitudes."

This recent study could contribute to the advancement of superconducting memory systems, potentially bringing them closer to their reliable deployment in real-world settings. In the future, the researchers' design could be improved further and scaled up to create even more reliable and highly performing memory systems.